The present invention relates generally to integrated circuits (ICs) and more particularly, to generating a routable layout pattern for placement of standard cells in an IC.
An IC layout pattern illustrates the placement positions of standard cells, including transistors, capacitors and the like, and the routing of interconnections (signal nets) between the standard cells. As a result of advances in the semiconductor technology, the complexity of ICs has increased considerably over the years such that contemporary ICs may contain several million transistors.
To design ICs having high degrees of complexity, various Electronic Design Automation (EDA) tools have been developed to automate the IC design process. Typically, the IC design process begins with an IC designer representing a logical IC design in the form of a netlist, i.e., a list of standard cells and nets interconnecting the standard cells. Thereafter, an EDA tool is used to place and route the standard cells, translating the logical IC design into a physical IC design, also known as a layout pattern. The IC designer specifies the value of standard cell density within a region of the IC. The value of standard cell density specified is such to prevent the occurrence of congestion zones or congestion hotspots in the IC layout design. However, though the EDA tool distributes standard cells ensuring the specified average standard cell density over the region of the IC, there may be localized zones within the IC that have a standard cell density in excess of the density specified by the IC designer. These localized regions of high standard cell density are sites having less available routing resources (routing tracks) as compared to the routing resources required. Examples of layout patterns are depicted and explained below in conjunction with FIGS. 1A and 1B.
One solution to the problem of formation of localized congestion hot spots is to ensure an even distribution of standard cells. An even distribution may be achieved using layout patterns as depicted in FIGS. 1A and 1B. FIGS. 1A and 1B illustrate schematic diagrams of conventional layout patterns 100 and 106. The conventional layout patterns 100, 106 include several placement regions 102 and several keep-out regions 104. Standard cells are placed in the placement regions 102 and the nets (interconnections) are routed through the keep-out regions 104. The layout pattern 100 depicted in FIG. 1A is known as a checkerboard pattern and the layout pattern 106 depicted in FIG. 1B is known as a diagonal keep-out layout pattern. It may be noted that alternating the placement regions 102 with keep-out regions 104 ensures an even standard cell density, which prevents the occurrence of congestion hot spots.
Though, the occurrence of localized congestion zones is prevented by the use of the above-described layout patterns, it is a difficult task to specify a standard cell density that ensures routability or a congestion free design. An inexperienced IC designer may require multiple iterations before realizing a layout pattern that is congestion free. To obtain a routable design, the IC designer inputs a value of standard cell density, such as 85%, to the EDA tool. The EDA tool generates a layout pattern based on the specified density value. The layout pattern is then observed for congestion zones. For example, if congestion zones are observed, the standard cell density is decreased by a suitable value, such as 5%, and the layout pattern is regenerated and analyzed for congestion zones. These steps are repeated until routability is obtained. Thus, the process of designing a congestion free layout pattern is a time-consuming, iterative process. It would be advantageous to be able to create a congestion free layout pattern without having to manually perform multiple layout iterations.